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t

RS

t

RH

A7 D7 D0

t

SSELHI

,

,

S

CLK

S

DATA

S

SEL

A7

D7 D0

S

CLK

S

DATA

S

SEL

90%

10%

90%

10%

t

SCLKR

t

SCLKF

t

SSELS

t

SCLK

t

SCLKL

t

WS

t

WH

t

SSELH

t

SCLKH

R/W

VDR

V

OCM

0

Differential

output signal

V

OCM

+ V

OD

/2

V

OCM

- V

OD

/2

ADC12EU050

SNAS444I –JANUARY 2008–REVISED APRIL 2013

www.ti.com

Figure 3. Output Level Definitions

Figure 4. SPI Write Timing

Figure 5. SPI Read Timing

12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated

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